Active Neutral Point Clamped Inverter, Zero-Crossing Switching Method And Zero-Crossing Switching Apparatus Thereof

ABSTRACT

An ANPC inverter, a zero-crossing switching method and a zero-crossing switching apparatus of the ANPC inverter are provided. The method includes: controlling switch states of switch devices in a bridge leg to change according to a preset logic when zero-crossing switching occurs in an output voltage instruction of the bridge leg, so as to prevent overvoltage in the switch device in the bridge leg. The preset logic includes switching among a sequence of switch state combinations. Switch state combinations of the switch devices before and after the zero-crossing switching occurs are defined as the first and second switch state combinations of the sequence. The second to the penultimate switch state combinations are all safe switch state combinations selected in advance, in each of which a maximum voltage borne by the switch devices in the bridge leg is clamped to a safe limit value.

CROSS REFERENCE TO RELATED APPLICATION

The present application claims the priority to Chinese PatentApplication No. 201710291639.3, titled “ACTIVE NEUTRAL POINT CLAMPEDINVERTER, ZERO-CROSSING SWITCHING METHOD AND ZERO-CROSSING SWITCHINGAPPARATUS THEREOF”, filed on Apr. 28, 2017 with the State IntellectualProperty Office of the People's Republic of China, which is incorporatedherein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates to the technical field of powerelectronics, and in particular to an active neutral point clampedinverter, a zero-crossing switching method of the active neutral pointclamped inverter and a zero-crossing switching apparatus of the activeneutral point clamped inverter BACKGROUND

As compared with a traditional neutral point clamped (NPC, diode neutralpoint clamped) inverter, an active neutral point clamped (ANPC) inverterincludes a controllable switch device to replace a clamping diode, so asto have a free system control and realize many control objectives.

FIG. 1 shows a topology of one bridge leg of an ANPC three-levelinverter. The bridge leg includes switch devices T1 to T6, in which T1,T2 and T5 are respectively an outer transistor, an inner transistor anda clamping transistor of an upper half bridge leg, and T4, T3 and T6 arerespectively an outer transistor, an inner transistor and a clampingtransistor of a lower half bridge leg. In order that the bridge legoutputs three levels including −u_(DC)/2, 0 and u_(DC)/2 (where u_(DC)is a direct-current bus voltage), a modulation scheme that the two innertransistors operate at a high frequency and the two outer transistorsand the two clamping transistors operate at a power frequency, isprovided in the conventional technology. As an example, FIG. 2 showswaveforms (not including a dead zone) of drive signals of the switchdevices in the modulation scheme, where u_(O)* represents an outputvoltage instruction of the bridge leg, and M2_gT1 to M2_gT6 representthe waveforms of the drive signals of T1 to T6 in one period of thepower frequency respectively.

With this modulation scheme, it can be ensured that a maximum voltageborne by the switch devices is u_(DC)/2 in a positive half period and anegative half period of an output voltage of the bridge leg. However,switch states of at least four switch devices in the bridge leg arerequired to change simultaneously (referring to a time t₀) whenzero-crossing switching occurs in u_(O)*. It is an ideal case thatswitching actions of the switch devices can be completed simultaneously,and the maximum voltage borne by T1 to T6 is still u_(DC)/2. In fact,some of the switching actions of the switch devices may be completedbefore others, which results in overvoltage risks of some switchdevices.

SUMMARY

In view of this, an ANPC inverter, a zero-crossing switching method ofthe ANPC inverter and a zero-crossing switching apparatus of the ANPCinverter are provided according to the present disclosure, so as toprevent an overvoltage phenomenon from occurring in switch devices inany bridge leg of the ANPC inverter when zero-crossing switching occursin an output voltage instruction of the bridge leg.

A zero-crossing switching method of an active neutral point clampedinverter is provided, which includes: acquiring an output voltageinstruction of a bridge leg of the active neutral point clampedinverter, determining whether zero-crossing switching occurs in theoutput voltage instruction; and controlling switch states of all ofswitch devices in the bridge leg to change according to a preset logic,in a case that the zero-crossing switching occurs in the output voltageinstruction.

The preset logic includes switching among a sequence of switch statecombinations. A switch state combination of all of the switch devices inthe bridge leg of the active neutral point clamped inverter before thezero-crossing switching occurs in the output voltage instruction of thebridge leg is defined as the first switch state combination of thesequence, and a switch state combination of all of the switch devices inthe bridge leg after the zero-crossing switching occurs in the outputvoltage instruction of the bridge leg is defined as the last switchstate combination of the sequence. In transition from the first switchstate combination to the last switch state combination. The secondswitch state combination to the penultimate switch state combination areall safe switch state combinations selected in advance, and in each ofthe safe switch state combination, a maximum voltage borne by the switchdevices in the bridge leg is clamped to a safe limit value.

The safe limit value is one-half of a direct-current bus voltage in acase that the zero-crossing switching method is applied to an activeneutral point clamped three-level inverter.

The safe switch state combinations include a switch state combination inwhich at least one clamping transistor in the bridge leg is switched onand a switch state combination in which only two inner transistors inthe bridge leg are switched on.

The switching among the sequence of switch state combinations includes:switching off one of the switch devices which is in a switched-on statein the previous switch state combination, or switching on one of theswitch devices which is in a switched-on state in the next switch statecombination.

A zero-crossing switching apparatus of an active neutral point clampedinverter is provided, which includes: an acquiring unit configured toacquire an output voltage instruction of a bridge leg of the activeneutral point clamped inverter; a determining unit configured todetermine whether zero-crossing switching occurs in the output voltageinstruction; and a switching control unit configured to control switchstates of all of switch devices in the bridge leg to change according toa preset logic, in a case that the determining unit determines that thezero-crossing switching occurs in the output voltage instruction.

The preset logic includes switching among a sequence of switch statecombinations. A switch state combination of all of the switch devices inthe bridge leg of the active neutral point clamped inverter before thezero-crossing switching occurs in the output voltage instruction of thebridge leg is defined as the first switch state combination of thesequence, and a switch state combination of all of the switch devices inthe bridge leg after the zero-crossing switching occurs in the outputvoltage instruction of the bridge leg is defined as the last switchstate combination of the sequence. In transition from the first switchstate combination to the last switch state combination. The secondswitch state combination to the penultimate switch state combination areall safe switch state combinations selected in advance, and in each ofthe safe switch state combinations, a maximum voltage borne by theswitch devices in the bridge leg is clamped to a safe limit value.

The safe limit value is one-half of a direct-current bus voltage in acase that the zero-crossing switching apparatus is applied to an activeneutral point clamped three-level inverter.

The safe switch state combinations include a switch state combination inwhich at least one clamping transistor in the bridge leg is switched onand a switch state combination in which only two inner transistors inthe bridge leg are switched on.

The switching among the sequence switch state combinations includes:switching off one of the switch devices which is in a switched-on statein the previous switch state combination, or switching on one of theswitch devices which is in a switched-on state in the next switch statecombination.

An active neutral point clamped inverter is provided, which includes anyone of the zero-crossing switching apparatuses of the active neutralpoint clamped inverter described above.

The active neutral point clamped inverter is an active neutral pointclamped three-level inverter or an active neutral point clampedfive-level inverter.

It can be seen from the above technical solutions that, in the presentdisclosure, when zero-crossing switching occurs in the output voltageinstruction of a bridge leg of the ANPC inverter, the switch states ofall of the switch devices in the bridge leg are not switched randomly,but switched according to the preset logic. In the preset logic, amaximum voltage borne by the switch devices in the bridge leg is clampedto the safe limit value in the switch state combination at any time,thereby preventing an overvoltage phenomenon from occurring in theswitch devices in the bridge leg during the zero-crossing switching.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to illustrate the technical solutions according to theembodiments of the present disclosure or in the conventional technologymore clearly, the drawings required in description of the embodiments orconventional technology are introduced simply below. Apparently, thedrawings in the following description show only some embodiments of thepresent disclosure, and other drawings may be obtained by those skilledin the art based on the provided drawings without creative work.

FIG. 1 is a schematic diagram showing a topology of one bridge leg in anANPC three-level inverter in conventional technology;

FIG. 2 is a schematic waveform diagram of drive signals of all of switchdevices in conventional technology;

FIG. 3 is a flowchart of a zero-crossing switching method of an ANPCinverter according to an embodiment of the present disclosure;

FIG. 4 is a schematic waveform diagram of drive signals of all of switchdevices operating at a power frequency according to an embodiment of thepresent disclosure; and

FIG. 5 is a schematic structural diagram of a zero-crossing switchingapparatus of an ANPC inverter according to an embodiment of the presentdisclosure.

DETAILED DESCRIPTION OF THE EMBODIMENTS

The technical solutions according to the embodiments of the presentdisclosure will be described clearly and completely below in conjunctionwith the drawings in the embodiments of the present disclosure. It isapparent that the described embodiments are only a part rather than allof the embodiments of the present disclosure. Any other embodimentsobtained by those skilled in the art without creative work based on theembodiments of the present disclosure fall within the protection scopeof the present disclosure.

Referring to FIG. 3, a zero-crossing switching method of an ANPCinverter is provided according to an embodiment of the presentdisclosure, to prevent an overvoltage phenomenon from occurring inswitch devices in any bridge leg of the ANPC inverter when zero-crossingswitching occurs in an output voltage instruction of the bridge leg. Thezero-crossing switching method of the ANPC inverter includes steps S01to S03.

In step S01, an output voltage instruction of a bridge leg of the ANPCinverter is acquired.

In step S02, whether zero-crossing switching occurs in the outputvoltage instruction is determined. The zero-crossing switching methodproceeds to step S03 in a case that the zero-crossing switching occursin the output voltage instruction, or the zero-crossing switching methodreturns to step S01 otherwise.

In step S03, switch states of all of switch devices in the bridge legare controlled to change according to a preset logic.

For convenience of description, a switch state combination of all of theswitch devices in a bridge leg of the ANPC inverter before thezero-crossing switching occurs in the output voltage instruction of thebridge leg and a switch state combination of all of the switch devicesin the bridge leg after the zero-crossing switching occurs in the outputvoltage instruction of the bridge leg are respectively defined as thefirst switch state combination and the last switch state combination.The preset logic includes switching among multiple switch statecombinations sequentially in transition from the first switch statecombination to the last switch state combination. The second switchstate combination to the penultimate switch state combination of themultiple switch state combinations are all safe switch statecombinations selected from all of switch state combinations of all ofthe switch devices in the bridge leg in advance. In each of the safeswitch state combinations, a maximum voltage borne by the switch devicesin the bridge leg is clamped to a safe limit value.

It can be known from the above description that, in the embodiment, whenzero-crossing switching occurs in the output voltage instruction of abridge leg of the ANPC inverter, the switch states of all of the switchdevices in the bridge leg are not switched randomly, but switchedaccording to the preset logic. In the preset logic, a maximum voltageborne by the switch devices in the bridge leg is always clamped to thesafe limit value in the switch state combination at any time, therebypreventing an overvoltage phenomenon from occurring in the switchdevices in the bridge leg during the zero-crossing switching.

The technical solution in the embodiment is described in detail belowwith the example of the bridge leg shown in FIG. 1.

The bridge leg shown in FIG. 1 includes 6 switch devices. System statesobtained when different numbers of switch devices are switched on areanalyzed, to search for the system state in which a maximum voltageborne by the switch devices in the bridge leg is clamped to U_(DC)/2. Aswitch state combination of all of the switch devices in the bridge legcorresponding to the found system state is a safe switch statecombination. In the analysis process, it is assumed hereinafter thateach of voltages of an upper voltage dividing capacitor and a lowervoltage dividing capacitor of a direct-current bus is u_(DC)/2.

1. A system state in a case that only one switch device in the bridgeleg shown in FIG. 1 is switched on is shown in Table 1.

TABLE 1 Switched-on Output voltage switch u_(o) of bridge leg Voltageborne by switch devices devices i_(o) > 0 i_(o) < 0 i_(o) > 0 i_(o) < 0T1 −u_(DC)/2 u_(DC)/2 u_(T1) = 0, u_(T2) = u_(DC) u_(T1) = 0, u_(T2) = 0u_(T3) = 0, u_(T4) = 0 u_(T3) + u_(T4) = u_(DC) T2 0 u_(DC)/2 u_(T1) =u_(DC)/2, u_(T2) = 0 u_(T1) = 0, u_(T2) = 0 u_(T3) + u_(T4) = u_(DC)/2u_(T3) + u_(T4) = u_(DC) T3 −u_(DC)/2 0 u_(T1) + u_(T2) = u_(DC)u_(T1) + u_(T2) = u_(DC)/2 u_(T3) = 0, u_(T4) = 0 u_(T3) = 0, u_(T4) = 0T4 −u_(DC)/2 u_(DC)/2 u_(T1) + u_(T2) = u_(DC) u_(T1) = 0, u_(T2) = 0u_(T3) = 0, u_(T4) = 0 u_(T3) = u_(DC), u_(T4) = 0 T5 −u_(DC)/2 0 u_(T1)= u_(DC)/2, u_(T2) = u_(DC)/2 u_(T1) = u_(DC)/2, u_(T2) = 0 u_(T3) = 0,u_(T4) = 0 u_(T3) + u_(T4) = u_(DC)/2 T6 0 −u_(DC)/2 u_(T1) + u_(T2) =u_(DC)/2 u_(T1) = 0, u_(T2) = 0 u_(T3) = 0, u_(T4) = u_(DC)/2 u_(T3) =u_(DC)/2, u_(T4) = u_(DC)/2

A case that only T1 is switched on is taken as an example. An outputvoltage of the bridge leg is u_(O)=−u_(DC)/2 in a case that a current ofthe bridge leg is l_(o)>0, in which case, a voltage borne by T1 isu_(T1)=0, a voltage borne by T2 is u_(T2)=u_(DC), a voltage borne by T3is u_(T3)=0, and a voltage borne by T4 is u_(T4)=0. u_(O)=u_(DC)/2 in acase of i_(o)<0, in which case, a voltage borne by T1 is u_(T1)=0, avoltage borne by T2 is u_(T2)=0, and a voltage borne by T3 and T4together is u_(T3)+u_(T4)=u_(DC). Because u_(T2)=u_(DC) occurs, that is,an overvoltage phenomenon occurs in T2, the switch state combinationthat only T1 is switched on cannot serve as a safe switch statecombination of all of the switch devices in the bridge leg. In addition,in a case of u_(T3)+u_(T4)=u_(DC), it is ideal that each of T3 and T4bears a voltage of u_(DC)/2. In practice, since there is always acertain difference between parameters of the switch devices, anovervoltage phenomenon that the voltage borne by one of T3 and T4 isgreater than u_(DC)/2 occurs in practice, which also confirms that theswitch state combination that only T1 is switched on cannot serve as asafe switch state combination of all of the switch devices in the bridgeleg.

It can be seen from Table 1 that, in the case that only one switchdevice is switched on, the switch state combination that only T5 or T6is switched on can serve as a safe switch state combination of all ofthe switch devices in the bridge leg, which is indicated in anunderlined manner in Table 1.

2. A system state in a case that two switch devices in the bridge legshown in FIG. 1 are both switched on is shown in Table 2.

In a case that two switch devices in the bridge leg shown in FIG. 1 areboth switched on, a condition that an outer transistor and a clampingtransistor at the same side are not both switched on should be met,otherwise a bus capacitor at the side is short-circuited. Therefore, thecases that “T1 and T5 are both switched on” and “T4 and T6 are bothswitched on” are not considered in Table 2.

TABLE 2 Switched-on Output voltage u_(o) switch of bridge leg Voltageborne by switch devices devices i_(o) > 0 i_(o) < 0 i_(o) > 0 i_(o) < 0T1, T2 u_(DC)/2 u_(DC)/2 u_(T1) = 0, u_(T2) = 0 u_(T1) = 0, u_(T2) = 0u_(T3) + u_(T4) = u_(DC) u_(T3) + u_(T4) = u_(DC) T1, T3 −u_(DC)/2 0u_(T1) = 0, u_(T2) = u_(DC) u_(T1) = 0, u_(T2) = u_(DC)/2 u_(T3) = 0,u_(T4) = 0 u_(T3) = 0, u_(T4) = u_(DC)/2 T1, T4 −u_(DC)/2 u_(DC) u_(T1)= 0, u_(T2) = u_(DC) u_(T1) = 0, u_(T2) = 0 u_(T3) = 0, u_(T4) = 0u_(T3) = u_(DC), u_(T4) = 0 T1, T6 0 u_(DC)/2 u_(T1) = 0, u_(T2) =u_(DC)/2 u_(T1) = 0, u_(T2) = 0 u_(T3) = 0, u_(T4) = u_(DC)/2 u_(T3) =u_(DC)/2, u_(T4) = u_(DC)/2 T2, T3 0 0 u_(T1) = u_(DC)/2, u_(T2) = 0u_(T1) = u_(DC)/2, u_(T2) = 0 u_(T3) = 0, u_(T4) = u_(DC)/2 u_(T3) = 0,u_(T4) = u_(DC)/2 T2, T4 0 u_(DC)/2 u_(T1) = u_(DC)/2, u_(T2) = 0 u_(T1)= 0, u_(T2) = 0 u_(T3) = u_(DC)/2, u_(T4) = 0 u_(T3) = u_(DC), u_(T4) =0 T2, T5 0 0 u_(T1) = u_(DC)/2, u_(T2) = 0 u_(T1) = u_(DC)/2, u_(T2) = 0u_(T3) + u_(T4) = u_(DC)/2 u_(T3) + u_(T4) = u_(DC)/2 T2, T6 0 u_(DC)/2u_(T1) = u_(DC)/2, u_(T2) = 0 u_(T1) = 0, u_(T2) = 0 u_(T3) = 0, u_(T4)= u_(DC)/2 u_(T3) = u_(DC)/2, u_(T4) = u_(DC)/2 T3, T4 −u_(DC)/2−u_(DC)/2 u_(T1) + u_(T2) = u_(DC) u_(T1) + u_(T2) = u_(DC) u_(T3) = 0,u_(T4) = 0 u_(T3) = 0, u_(T4) = 0 T3, T5 −u_(DC)/2 0 u_(T1) = u_(DC)/2,u_(T2) = u_(DC)/2 u_(T1) = u_(DC)/2, u_(T2) = 0 u_(T3) = 0, u_(T4) = 0u_(T3) = 0, u_(T4) = u_(DC)/2 T3, T6 0 0 u_(T1) + u_(T2) = u_(DC)/2u_(T1) + u_(T2) = u_(DC)/2 u_(T3) = 0, u_(T4) = u_(DC)/2 u_(T3) = 0,u_(T4) = u_(DC)/2 T4, T5 −u_(DC)/2 0 u_(T1) = u_(DC)/2, u_(T2) =u_(DC)/2 u_(T1) = u_(DC)/2, u_(T2) = 0 u_(T3) = 0, u_(T4) = 0 u_(T3) =u_(DC)/2, u_(T4) = 0 T5, T6 0 0 u_(T1) = u_(DC)/2, u_(T2) = 0 u_(T1) =u_(DC)/2, u_(T2) = 0 u_(T3) = 0, u_(T4) = u_(DC)/2 u_(T3) = 0, u_(T4) =u_(DC)/2

It can been seen from Table 2 that, in a case that only two switchdevices are switched on, the switch state combinations that “T1 and T6are both switched on”, “T2 and T3 are both switched on”, “T2 and T5 areboth switched on”, “T2 and T6 are both switched on”, “T3 and T5 are bothswitched on”, “T3 and T6 are both switched on”, “T4 and T5 are bothswitched on” and “T5 and T6 are both switched on” may serve as safeswitch state combinations of all of the switch devices in the bridgeleg, which are indicated in an underlined manner in Table 2.

3. A system state in a case that three switch devices in the bridge legshown in FIG. 1 are all switched on is shown in Table 3.

In a case that the three switch devices in the bridge leg shown in FIG.1 are all switched on, in addition to the condition that the outertransistor and the clamping transistor at the same side are not bothswitched on, a condition that two outer transistors and one innertransistor are not all switched on and two inner transistors and oneouter transistor are not all switched on should be met, otherwise it isinevitable that one of the switch devices directly bears adirect-current bus voltage u_(DC). Therefore, the cases that “T1 and T5are both switched on”, “T4 and T6 are both switched on” and “any threeof T1 to T4 are all switched on” are not considered in Table 3.

TABLE 3 Switched-on Output voltage u_(o) switch of bridge leg Voltageborne by switch devices devices i_(o) > 0 i_(o) < 0 i_(o) > 0 i_(o) < 0T1, T2, T6 u_(DC)/2 u_(DC)/2 u_(T1) = 0, u_(T2) = 0 u_(T1) = 0, u_(T2) =0 u_(T3) = u_(DC)/2, u_(T4) = u_(DC)/2 u_(T3) = u_(DC)/2, u_(T4) =u_(DC)/2 T1, T3, T6 0 0 u_(T1) = 0, u_(T2) = u_(DC)/2 u_(T1) = 0, u_(T2)= u_(DC)/2 u_(T3) = 0, u_(T4) = u_(DC)/2 u_(T3) = 0, u_(T4) = u_(DC)/2T2, T3, T5 0 0 u_(T1) = u_(DC)/2, u_(T2) = 0 u_(T1) = u_(DC)/2, u_(T2) =0 u_(T3) = 0, u_(T4) = u_(DC)/2 u_(T3) = 0, u_(T4) = u_(DC)/2 T2, T3, T60 0 u_(T1) = u_(DC)/2, u_(T2) = 0 u_(T1) = u_(DC)/2, u_(T2) = 0 u_(T3) =0, u_(T4) = u_(DC)/2 u_(T3) = 0, u_(T4) = u_(DC)/2 T2, T4, T5 0 0 u_(T1)= u_(DC)/2, u_(T2) = 0 u_(T1) = u_(DC)/2, u_(T2) = 0 u_(T3) = 0, u_(T4)= u_(DC)/2 u_(T3) = 0, u_(T4) = u_(DC)/2 T2, T5, T6 0 0 u_(T1) =u_(DC)/2, u_(T2) = 0 u_(T1) = u_(DC)/2, u_(T2) = 0 u_(T3) = 0, u_(T4) =u_(DC)/2 u_(T3) = 0, u_(T4) = u_(DC)/2 T3, T4, T5 −u_(DC)/2 −u_(DC)/2u_(T1) = u_(DC)/2, u_(T2) = u_(DC)/2 u_(T1) = u_(DC)/2, u_(T2) =u_(DC)/2 u_(T3) = 0, u_(T4) = 0 u_(T3) = 0, u_(T4) = 0 T3, T5, T6 0 0u_(T1) = u_(DC)/2, u_(T2) = 0 u_(T1) = u_(DC)/2, u_(T2) = 0 u_(T3) = 0,u_(T4) = u_(DC)/2 u_(T3) = 0, u_(T4) = u_(DC)/2

It can be seen from Table 3 that each of the switch state combinationslisted in Table 3 is a safe switch state combination, which areindicated in an underlined manner in the Table 3.

4. In a case that four switch devices in the bridge leg shown in FIG. 1are all switched on, only one switch state combination that T2, T3, T5and T6 are all switched on is a safe switch state combination. In suchcase, an output voltage of the bridge leg is u_(O)=0, and voltages borneby the switch devices are: u_(T1)=u_(DC)/2, u_(T2)=0, u_(T3)=0, andu_(T4)=u_(DC)/2.

5. The bus capacitor is short-circuited in a case that five or moreswitch devices in the bridge leg shown in FIG. 1 are all switched on,and therefore there is no safe switch state combination.

6. There is no safe switch state combination in a case that no switchdevice in the bridge leg shown in FIG. 1 is switched on, for the reasonas follows.

In a case that no switch device in the bridge leg shown in FIG. 1 isswitched on, which switch device has a switched-on antiparallel diode isdetermined by a freewheeling circuit. In a case that i_(o) flows outfrom point O, antiparallel diodes of T3 and T4 are switched on, avoltage at point O is equal to a negative bus voltage, and T1 and T2bear the direct-current bus voltage u_(DC) together. Since anantiparallel diode of T5 is not switched on, a level at point a isunknown. If there is a difference between parasite parameters of thetransistors T1 and T2, it cannot be ensured that each of T1 and T2 bearsa voltage of u_(DC)/2, that is, there is no safe switch statecombination. Similarly, a case that i_(o) flows into point O can beanalyzed.

In summary, all of the safe switch state combinations of all of theswitch devices in the bridge leg shown in FIG. 1 are enumerated in Table4.

TABLE 4 The number of switched-on transistor devices 1 2 3 4 Switched-onT5; T1, T6; T1, T2, T6; T2, T3, T5, transistor T6; T2, T3; T1, T3, T6;T6; devices T2, T5; T2, T3, T5; T2, T6; T2, T3, T6; T3, T5; T2, T4, T5;T3, T6; T2, T5, T6; T4, T5; T3, T4, T5; T5, T6; T3, T5, T6;

It can be known from the above description that, in a case that the ANPCinverter is an ANPC three-level inverter, a safe switch statecombination of all the switch devices in a bridge leg refers to a switchstate combination in which a maximum voltage borne by the switch devicesis clamped to u_(DC)/2. Based on this criterion, a switch statecombination that at least one clamping transistor in the bridge leg isswitched on and a switch state combination that only two innertransistors in the bridge leg are switched on may be selected as safeswitch state combinations.

When positive-to-negative zero-crossing switching occurs in the outputvoltage instruction of the bridge leg shown in FIG. 1, it can be knownfrom FIG. 2 that T1 and T6 are both switched on in the first switchstate combination, and T4 and T5 are all switched on in the last stageswitch state combination. Therefore, switching actions to be completedduring the zero-crossing switching includes: switching off T1 and T6 andswitching on T4 and T5. Since a switch state of only one switch devicecan be changed at a time instant, it can be known from Table 4 that, inthe positive-to-negative zero-crossing switching, a switching amongmultiple switch state combinations may be switching from “T1, T6” (thefirst switch state combination) to “T6” (the second switch statecombination), then to “T5, T6” (the third switch state combination),then to “T5” (the fourth switch state combination), and then to “T4, T5”(the last switch state combination).

When negative-to-positive zero-crossing switching occurs in the outputvoltage instruction of the bridge leg shown in FIG. 1, it can be knownfrom FIG. 2 that T4 and T5 are both switched on in the first switchstate combination, and T1 and T6 are both switched on in the last switchstate combination. Therefore, switching actions to be completed in thezero-crossing switching includes: switching off T4 and T5 and switchingon T1 and T6. Since a switch state of only one switch device can bechanged at a time instant, it can be known from Table 4 that, in thenegative-to-positive zero-crossing switching, a switching among multipleswitch state combinations may be switching from “T4, T5” (the firstswitch state combination) to “T5” (the second switch state combination),then to “T5, T6” (the third switch state combination), then to “T6” (thefourth switch state combination), and then to “T1, T6” (the last switchstate combination).

Corresponding to the above switching manners of the multiple switchstate combinations. FIG. 4 shows waveforms (g_present_T1, g_present_T4,g_present_T5 and g_present_T6 represent waveforms of drive signals ofT1, T4, T5 and T6 respectively) of drive signals of all of switchdevices operating at a power frequency. The switching time areillustrated as follows.

(1) In a case that positive-to-negative zero-crossing switching occursin the output voltage instruction of the bridge leg shown in FIG. 1, T1is first switched off at a time t11, then T5 is switched on at a timet112, then T6 is switched off at a time t13, and finally T4 is switchedon at a time 114.

(2) In a case that negative-to-positive zero-crossing switching occursin the output voltage instruction of the bridge leg shown in FIG. 1, T4is first switched off at a time t21, then T6 is switched on at a timet22, then T5 is switched off at a time t23, and finally T1 is switchedon at a time t24.

The magnitude of an output voltage of the bridge leg in thezero-crossing switching is related to switch states of thehigh-frequency switch devices T2 and T3, which is shaded in FIG. 4.

Extending the above switching manner of the multiple switch statecombinations to be applied in any type of ANPC inverter, the switchingmanner may be switching off one switch device which is in a switched-onstate in a previous switch state combination, or switching on one switchdevice which is in a switched-on in a next switch state combination.

It should be noted that the above switching manner of the multipleswitch state combinations is only an example, and other switching mannermay also be adopted. For example, when positive-to-negativezero-crossing switching occurs in the output voltage instruction of thebridge leg shown in FIG. 1, the switching manner of the multiple switchstate combinations may also be switching from “T1, T2, T6” (the firststage switch state combination) to “T2, T6” (the second switch statecombination), then to “T2, T5, T6” (the third switch state combination),then to “T2, T5” (the fourth switch state combination), and finally to“T2, T4, T5” (the last switch state combination). Whennegative-to-positive zero-crossing switching occurs in the outputvoltage instruction of the bridge leg shown in FIG. 1, the switchingmanner of the multiple switch state combinations may also be switchingfrom “T2, T4, T5” (the first switch state combination) to “T2, T5” (thesecond switch state combination), then to “T2, T5, T6” (the third switchstate combination), then to “T2, T6” (the fourth switch statecombination), and finally to “T1, T2, T6” (the last switch statecombination).

Referring to FIG. 5, a zero-crossing switching apparatus of an ANPCinverter is further provided according to an embodiment of the presentdisclosure, which includes an acquiring unit 100, a determining unit 200and a switching control unit 300.

The acquiring unit 100 is configured to acquire an output voltageinstruction of a bridge leg of the ANPC inverter.

The determining unit 200 is configured to determine whetherzero-crossing switching occurs in the output voltage instruction.

The switching control unit 300 is configured to control switch states ofall of switch devices in the bridge leg to change according to a presetlogic, in a case that the determining unit 200 determines that thezero-crossing switching occurs in the output voltage instruction.

Specifically, a switch state combination of all of the switch devices ina bridge leg of the ANPC inverter before the zero-crossing switchingoccurs in the output voltage instruction of the bridge leg and a switchstate combination of all of the switch devices in the bridge leg afterthe zero-crossing switching occurs in the output voltage instruction ofthe bridge leg are respectively defined as the first switch statecombination and the last switch state combination. The preset logicincludes switching among multiple switch state combinations sequentiallyin transition from the first switch state combination to the last switchstate combination. The second switch state combination to thepenultimate switch state combination of the multiple switch statecombinations are safe switch state combinations selected from all ofswitch state combinations of all of the switch devices in the bridge legin advance. In each of the safe switch state combinations, a maximumvoltage borne by the switch devices in the bridge leg is clamped to asafe limit value.

The safe limit value is one-half of a direct-current bus voltage in acase that the zero-crossing switching apparatus is applied to an ANPCthree-level inverter.

The safe switch state combination includes a switch state combination inwhich at least one clamping transistor in the bridge leg is switched onand a switch state combination in which only two inner transistors inthe bridge leg are switched on.

The switching among the multiple switch state combinations includes:switching off one switch device which is in a switched-on state in theprevious switch state combination, or switching on one switch devicewhich is in a switched-on state in the next switch state combination.

In addition, an ANPC inverter is further provided according to anembodiment of the present disclosure, which includes any one of thezero-crossing switching apparatus of the ANCP inverter described above.The ANPC inverter may be an ANPC three-level inverter or an ANPCfive-level inverter, which is not limited herein.

In summary, in the present disclosure, when zero-crossing switchingoccurs in the output voltage instruction of a bridge leg of the ANPCinverter, the switch states of all of the switch devices in the bridgeleg are not switched randomly, but switched according to the presetlogic. In the preset logic, a maximum voltage borne by the switchdevices in the bridge leg is always clamped to the safe limit value inthe switch state combination at any time, thereby preventing anovervoltage phenomenon from occurring in the switch devices in thebridge leg during the zero-crossing switching.

The embodiments of the present disclosure are described in a progressivemanner, and each embodiment is focused on describing difference fromother embodiments, and reference may be made one to another for the sameor similar parts among the embodiments.

Since the apparatus disclosed in the embodiment corresponds to themethod disclosed in the embodiment, the description for the apparatus issimple, and reference may be made to the method in the embodiment forthe relevant parts.

Based on the above description of the embodiments, those skilled in theart can implement or use the present disclosure. Numerous modificationsto the embodiments are apparent to those skilled in the art, and thegeneral principles defined herein can be implemented in otherembodiments without deviating from the spirit or scope of the presentdisclosure. Therefore, the present disclosure is not limited to theembodiments described herein, but conforms to the widest scopeconsistent with the principles and novel features disclosed herein.

1. A zero-crossing switching method of an active neutral point clampedinverter, comprising; acquiring an output voltage instruction of abridge leg of the active neutral point clamped inverter; determiningwhether zero-crossing switching occurs in the output voltageinstruction; and controlling switch states of all of switch devices inthe bridge leg to change according to a preset logic, in a case that thezero-crossing switching occurs in the output voltage instruction;wherein the preset logic comprises switching among a sequence of switchstate combinations, a switch state combination of all of the switchdevices in the bridge leg of the active neutral point clamped inverterbefore the zero-crossing switching occurs in the output voltageinstruction of the bridge leg is defined as the first switch statecombination of the sequence, and a switch state combination of all ofthe switch devices in the bridge leg after the zero-crossing switchingoccurs in the output voltage instruction of the bridge leg is defined asthe last switch state combination of the sequence, and in transitionfrom the first switch state combination to the last switch statecombination, the second switch state combination to the penultimateswitch state combination are all safe switch state combinations selectedin advance, and in each of the safe switch state combinations, a maximumvoltage borne by the switch devices in the bridge leg is clamped to asafe limit value.
 2. The zero-crossing switching method of the activeneutral point clamped inverter according to claim 1, wherein the safelimit value is one-half of a direct-current bus voltage in a case thatthe zero-crossing switching method is applied to an active neutral pointclamped three-level inverter.
 3. The zero-crossing switching method ofthe active neutral point clamped inverter according to claim 2, whereinthe safe switch state combinations comprise: a switch state combinationin which at least one clamping transistor in the bridge leg is switchedon, and a switch state combination in which only two inner transistorsin the bridge leg are switched on.
 4. The zero-crossing switching methodof the active neutral point clamped inverter according to claim 1,wherein the switching among the sequence of switch state combinationscomprises: switching off one of the switch devices which is in aswitched-on state in the previous switch state combination; or switchingon one of the switch devices which is in a switched-on state in the nextswitch state combination.
 5. A zero-crossing switching apparatus of anactive neutral point clamped inverter, comprising: an acquiring unitconfigured to acquire an output voltage instruction of a bridge leg ofthe active neutral point clamped inverter; a determining unit configuredto determine whether zero-crossing switching occurs in the outputvoltage instruction; and a switching control unit configured to controlswitch states of all of switch devices in the bridge leg to changeaccording to a preset logic, in a case that the determining unitdetermines that the zero-crossing switching occurs in the output voltageinstruction; wherein the preset logic comprises switching among asequence of switch state combinations, a switch state combination of allof the switch devices in the bridge leg of the active neutral pointclamped inverter before the zero-crossing switching occurs in the outputvoltage instruction of the bridge leg is defined as the first switchstate combination of the sequence, and a switch state combination of allof the switch devices in the bridge leg after the zero-crossingswitching occurs in the output voltage instruction of the bridge leg isdefined as the last switch state combination of the sequence, and intransition from the first switch state combination to the last switchstate combination, the second switch state combination to thepenultimate switch state combination are all safe switch statecombinations selected in advance, and in each of the safe switch statecombinations, a maximum voltage borne by the switch devices in thebridge leg is clamped to a safe limit value.
 6. The zero-crossingswitching apparatus of the active neutral point clamped inverteraccording to claim 5, wherein the safe limit value is one-half of adirect-current bus voltage in a case that the zero-crossing switchingapparatus is applied to an active neutral point clamped three-levelinverter.
 7. The zero-crossing switching apparatus of an active neutralpoint clamped inverter according to claim 6, wherein the safe switchstate combinations comprise: a switch state combination in which atleast one clamping transistor in the bridge leg is switched on, and aswitch state combination in which only two inner transistors in thebridge leg are switched on.
 8. The zero-crossing switching apparatus ofthe active neutral point clamped inverter according to claim 5, whereinthe switching among the sequence of the switch state combinationscomprises: switching off one of the switch devices which is in aswitched-on state in the previous switch state combination; or switchingon one of the switch devices which is in a switched-on state in the nextswitch state combination.
 9. An active neutral point clamped inverter,comprising a zero-crossing switching apparatus, wherein thezero-crossing switching apparatus comprises: an acquiring unitconfigured to acquire an output voltage instruction of a bridge leg ofthe active neutral point clamped inverter; a determining unit configuredto determine whether zero-crossing switching occurs in the outputvoltage instruction; and a switching control unit configured to controlswitch states of all of switch devices in the bridge leg to changeaccording to a preset logic, in a case that the determining unitdetermines that the zero-crossing switching occurs in the output voltageinstruction; wherein the preset logic comprises switching among asequence of switch state combinations, a switch state combination of allof the switch devices in the bridge leg of the active neutral pointclamped inverter before the zero-crossing switching occurs in the outputvoltage instruction of the bridge leg is defined as the first switchstate combination of the sequence, and a switch state combination of allof the switch devices in the bridge leg after the zero-crossingswitching occurs in the output voltage instruction of the bridge leg isdefined as the last switch state combination of the sequence, and intransition from the first switch state combination to the last switchstate combination, the second switch state combination to thepenultimate switch state combination are all safe switch statecombinations selected in advance, and in each of the safe switch statecombinations, a maximum voltage borne by the switch devices in thebridge leg is clamped to a safe limit value.
 10. The active neutralpoint clamped inverter according to claim 9, wherein the active neutralpoint clamped inverter is an active neutral point clamped three-levelinverter or an active neutral point clamped five-level inverter.
 11. Theactive neutral point clamped inverter according to claim 9, wherein thesafe limit value is one-half of a direct-current bus voltage in a casethat the active neutral point clamped inverter is an active neutralpoint clamped three-level inverter.
 12. The active neutral point clampedinverter according to claim 11, wherein the safe switch statecombinations comprise: a switch state combination in which at least oneclamping transistor in the bridge leg is switched on, and a switch statecombination in which only two inner transistors in the bridge leg areswitched on.
 13. The active neutral point clamped inverter according toclaim 9, wherein the switching among the sequence of the switch statecombinations comprises: switching off one of the switch devices which isin a switched-on state in the previous switch state combination; orswitching on one of the switch devices which is in a switched-on statein the next switch state combination.